[PATCH pve-docs] vcpu-types: Update CPU models

[PATCH pve-docs] vcpu-types: Update CPU models

[Jonas Theisen]

Updated list of virtual CPU models of QEMU to the current state
based on pve-qemu-kvm 11.0.3-3

Signed-off-by: Jonas Theisen <j.theisen@proxmox.com>
---
 qm-vcpu-list.adoc | 83 +++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 81 insertions(+), 2 deletions(-)

diff --git a/qm-vcpu-list.adoc b/qm-vcpu-list.adoc
index 2aa1bfd..9ea968a 100644
--- a/qm-vcpu-list.adoc
+++ b/qm-vcpu-list.adoc
@@ -75,8 +75,64 @@ https://en.wikipedia.org/wiki/List_of_Intel_Xeon_processors[Intel processors]
 +
 * 'Icelake-v6' : add "5-level EPT" ('+vmx-page-walk-5')
 +
+* 'Icelake-v7' : re-enable TSX ('+hle', '+rtm')
++
 * 'SapphireRapids' : https://en.wikipedia.org/wiki/Sapphire_Rapids[4th generation Xeon Scalable server processors]
-
++
+* 'SapphireRapids-v2' : add "Fill Buffer Stale Data Propagator (FBSDP)" mitigation ('+fbsdp-no'),
+"Primary Stale Data Propagator (PSDP)" mitigation ('+psdp-no'),
+"Shared Buffers Data Read (SBDR)", "Stale Data Propagator (SSDP)" mitigation ('+sbdr-ssdp-no")
++
+* 'SapphireRapids-v3' : add "Stack segment" ('+ss'), "Cache Line Demote" ('+cldemote'),
+"TSC adjust" ('+tsc-adjust','+tsc_adjust'), "Move Doubleword as Direct Store" ('+movdiri', '+movdir64b')
++
+* 'SapphireRapids-v4' : expose "Intel 0x1F CPUID leaf" ('+x-force-cpuid-0x1f'),
+remove "legacy-cache" ('-legacy-cache')
++
+* 'SapphireRapids-v5' : add CET IBT and SS ('+cet-ibt','+cet-ss')
++
+* 'SapphireRapids-v6' : add "ITS" mitigation ('+its-no')
++
+* 'SierraForest' : https://en.wikipedia.org/wiki/Sierra_Forest[6th generation Xeon Scalable server processors with E-cores]
++
+* 'SierraForest-v2' : add "Register File Data Sampling (RFDS)" mitigation ('+rfds-no'),
+"Fast Store Forwarding Predictor (FSFP)" ('+intel-psfd'),
+"Gather Data Sampling (GDS)" mitigation ('+gds-no'),
+"Stack segment" ('+ss'), "Cache Line Demote" ('+cldemote'),
+"Linear Address Masking (LAM)" ('+lam'),
+"TSC adjust" ('+tsc-adjust','+tsc_adjust'),
+"Indirect Predictor Control" ('+ipred-ctrl'),
+"Move Doubleword as Direct Store" ('+movdiri', '+movdir64b'),
+"Branch History Injection Control" ('+bhi-ctrl'),
+"Restricted Return Stack Buffer Alternate (RRSBA)" ('+rrsba-ctrl'),
+change 'stepping' from '0' to '3'
++
+* 'SierraForest-v3' : expose "Intel 0x1F CPUID leaf" ('+x-force-cpuid-0x1f'), remove "legacy-cache" ('-legacy-cache')
++
+* 'SierraForest-v4' : add CET IBT and SS ('+cet-ibt','+cet-ss')
++
+* 'SierraForest-v5' : add "ITS" mitigation ('+its-no')
++
+* 'GraniteRapids' : https://en.wikipedia.org/wiki/Granite_Rapids[6th generation Xeon Scalable server processors with P-cores]
++
+* 'GraniteRapids-v2' : add AVX10 flags ('avx10', '+avx10-version', '+avx10-128', '+avx10-256', '+avx10-512'),
+"Stack segment" ('+ss'), "Cache Line Demote" ('+cldemote'),
+"TSC adjust" ('+tsc-adjust','+tsc_adjust'),
+"Move Doubleword as Direct Store" ('+movdiri', '+movdir64b'),
+change 'stepping' from '0' to '1', 'level' and 'min-level' from '32' to '36'
++
+* 'GraniteRapids-v3' : expose "Intel 0x1F CPUID leaf" ('+x-force-cpuid-0x1f'), remove "legacy-cache" ('-legacy-cache')
++
+* 'GraniteRapids-v4' : add CET IBT and SS ('+cet-ibt','+cet-ss')
++
+* 'GraniteRapids-v5' : add "ITS" mitigation ('+its-no')
++
+* 'ClearwaterForest': https://en.wikipedia.org/wiki/Clearwater_Forest[6+ generation Xeon Scalable server processors with E-cores]
++
+* 'ClearwarterForest-v2' : add CET IBT and SS ('+cet-ibt','+cet-ss')
++
+* 'ClearwarterForest-v3' : add "ITS" mitigation ('+its-no'),
+expose "Intel 0x1F CPUID leaf" ('+x-force-cpuid-0x1f'), remove "legacy-cache" ('-legacy-cache')
 
 AMD CPU Types
 -------------
@@ -96,13 +152,36 @@ https://en.wikipedia.org/wiki/List_of_AMD_processors[AMD processors]
 * 'EPYC-v3' : add missing flags ('+perfctr-core', '+clzero', '+xsaveerptr',
 '+xsaves')
 +
+* 'EPYC-v4' : no changes
++
+* 'EPYC-v5' : add "Software Uncorrectable Error Containment and Recovery capability" ('+succor'),
+"Machine Check Architecture (MCA) overflow recovery" ('+overflow-recov')
++
 * 'EPYC-Rome' : https://en.wikipedia.org/wiki/Zen_2[2nd generation of Zen processors]
 +
 * 'EPYC-Rome-v2' : add Spectre v2, v4 protection ('+ibrs', '+amd-ssbd')
 +
+* 'EPYC-Rome-v3' : no changes
++
+* 'EPYC-Rome-v4' : remove "XSAVES" ('-xsaves')
++
+* 'EPYC-Rome-v5' : add "Software Uncorrectable Error Containment and Recovery capability" ('+succor'),
+"Machine Check Architecture (MCA) overflow recovery" ('+overflow-recov')
++
 * 'EPYC-Milan' : https://en.wikipedia.org/wiki/Zen_3[3rd generation of Zen processors]
 +
 * 'EPYC-Milan-v2' : add missing flags ('+vaes', '+vpclmulqdq',
 '+stibp-always-on', '+amd-psfd', '+no-nested-data-bp',
 '+lfence-always-serializing', '+null-sel-clr-base')
-
++
+* 'EPYC-Milan-v3' : add "Software Uncorrectable Error Containment and Recovery capability" ('+succor'),
+"Machine Check Architecture (MCA) overflow recovery" ('+overflow-recov')
++
+* 'EPYC-Genoa' : https://en.wikipedia.org/wiki/Zen_4[4th generation Zen processors]
++
+* 'EPYC-Genoa-v2' : add "Software Uncorrectable Error Containment and Recovery capability" ('+succor'),
+"Machine Check Architecture (MCA) overflow recovery" ('+overflow-recov'),
+"AMD Performance Monitoring Version 2" ('+perfmon-v2'),
+"Support for FS and GS access from user space" ('+fs-gs-base-ns')
++
+* 'EPYC-Turin' : https://en.wikipedia.org/wiki/Zen_5[5th generation Zen processors]
-- 
2.47.3