* [pve-devel] [PATCH qemu-server] close #6378: expose guest-phys-bits CPU option
@ 2025-08-12 15:30 Fiona Ebner
2025-08-13 7:34 ` [pve-devel] applied: " Fabian Grünbichler
0 siblings, 1 reply; 2+ messages in thread
From: Fiona Ebner @ 2025-08-12 15:30 UTC (permalink / raw)
To: pve-devel
Quoting Fabian Grünbichler from the bug report:
> Intel ships some CPUs where the CPU address width and the IOMMU
> address width are different, which requires setting that option to
> properly support huge pages and/or VFIO:
>
> https://bugzilla.kernel.org/show_bug.cgi?id=220057
> https://lore.kernel.org/all/20250502224035.3183451-1-alex.williamson@redhat.com/t
> https://lore.kernel.org/qemu-devel/20250130134346.1754143-1-clg@redhat.com/
This likely also gives users a way forward with a regression reported
in the community forum:
https://forum.proxmox.com/threads/169586/
Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
---
src/PVE/QemuServer/CPUConfig.pm | 31 +++++++++++++------
.../q35-viommu-intel-guest-phys-bits.conf | 2 ++
.../q35-viommu-intel-guest-phys-bits.conf.cmd | 25 +++++++++++++++
3 files changed, 48 insertions(+), 10 deletions(-)
create mode 100644 src/test/cfg2cmd/q35-viommu-intel-guest-phys-bits.conf
create mode 100644 src/test/cfg2cmd/q35-viommu-intel-guest-phys-bits.conf.cmd
diff --git a/src/PVE/QemuServer/CPUConfig.pm b/src/PVE/QemuServer/CPUConfig.pm
index 1c7c12fc..786a99d8 100644
--- a/src/PVE/QemuServer/CPUConfig.pm
+++ b/src/PVE/QemuServer/CPUConfig.pm
@@ -223,6 +223,13 @@ my $cpu_fmt = {
pattern => qr/$cpu_flag_any_re(;$cpu_flag_any_re)*/,
optional => 1,
},
+ 'guest-phys-bits' => {
+ type => 'integer',
+ minimum => 32, # see target/i386/cpu.c in QEMU
+ maximum => 64,
+ description => "Number of physical address bits available to the guest.",
+ optional => 1,
+ },
'phys-bits' => {
type => 'string',
format => 'pve-phys-bits',
@@ -680,18 +687,22 @@ sub get_cpu_options {
$pve_forced_flags,
);
- my $phys_bits = '';
- foreach my $conf ($custom_cpu, $cpu) {
- next if !defined($conf);
- my $conf_val = $conf->{'phys-bits'};
- next if !$conf_val;
- if ($conf_val eq 'host') {
- $phys_bits = ",host-phys-bits=true";
- } else {
- $phys_bits = ",phys-bits=$conf_val";
+ for my $phys_bits_opt (qw(guest-phys-bits phys-bits)) {
+ my $phys_bits = '';
+ foreach my $conf ($custom_cpu, $cpu) {
+ next if !defined($conf);
+ my $conf_val = $conf->{$phys_bits_opt};
+ next if !$conf_val;
+ if ($conf_val eq 'host') {
+ die "unexpected value 'host' for guest-phys-bits"
+ if $phys_bits_opt eq 'guest-phys-bits';
+ $phys_bits = ",host-phys-bits=true";
+ } else {
+ $phys_bits = ",${phys_bits_opt}=${conf_val}";
+ }
}
+ $cpu_str .= $phys_bits;
}
- $cpu_str .= $phys_bits;
return ('-cpu', $cpu_str);
}
diff --git a/src/test/cfg2cmd/q35-viommu-intel-guest-phys-bits.conf b/src/test/cfg2cmd/q35-viommu-intel-guest-phys-bits.conf
new file mode 100644
index 00000000..7decb63e
--- /dev/null
+++ b/src/test/cfg2cmd/q35-viommu-intel-guest-phys-bits.conf
@@ -0,0 +1,2 @@
+machine: q35,viommu=intel
+cpu: host,guest-phys-bits=39
diff --git a/src/test/cfg2cmd/q35-viommu-intel-guest-phys-bits.conf.cmd b/src/test/cfg2cmd/q35-viommu-intel-guest-phys-bits.conf.cmd
new file mode 100644
index 00000000..b24baeb0
--- /dev/null
+++ b/src/test/cfg2cmd/q35-viommu-intel-guest-phys-bits.conf.cmd
@@ -0,0 +1,25 @@
+/usr/bin/kvm \
+ -id 8006 \
+ -name 'vm8006,debug-threads=on' \
+ -no-shutdown \
+ -chardev 'socket,id=qmp,path=/var/run/qemu-server/8006.qmp,server=on,wait=off' \
+ -mon 'chardev=qmp,mode=control' \
+ -chardev 'socket,id=qmp-event,path=/var/run/qmeventd.sock,reconnect-ms=5000' \
+ -mon 'chardev=qmp-event,mode=control' \
+ -pidfile /var/run/qemu-server/8006.pid \
+ -daemonize \
+ -smp '1,sockets=1,cores=1,maxcpus=1' \
+ -nodefaults \
+ -boot 'menu=on,strict=on,reboot-timeout=1000,splash=/usr/share/qemu-server/bootsplash.jpg' \
+ -vnc 'unix:/var/run/qemu-server/8006.vnc,password=on' \
+ -cpu 'host,+kvm_pv_eoi,+kvm_pv_unhalt,guest-phys-bits=39' \
+ -m 512 \
+ -global 'ICH9-LPC.disable_s3=1' \
+ -global 'ICH9-LPC.disable_s4=1' \
+ -device 'intel-iommu,intremap=on,caching-mode=on' \
+ -readconfig /usr/share/qemu-server/pve-q35-4.0.cfg \
+ -device 'usb-tablet,id=tablet,bus=ehci.0,port=1' \
+ -device 'VGA,id=vga,bus=pcie.0,addr=0x1' \
+ -device 'virtio-balloon-pci,id=balloon0,bus=pci.0,addr=0x3,free-page-reporting=on' \
+ -iscsi 'initiator-name=iqn.1993-08.org.debian:01:aabbccddeeff' \
+ -machine 'type=q35+pve0,kernel-irqchip=split'
--
2.47.2
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^ permalink raw reply [flat|nested] 2+ messages in thread
* [pve-devel] applied: [PATCH qemu-server] close #6378: expose guest-phys-bits CPU option
2025-08-12 15:30 [pve-devel] [PATCH qemu-server] close #6378: expose guest-phys-bits CPU option Fiona Ebner
@ 2025-08-13 7:34 ` Fabian Grünbichler
0 siblings, 0 replies; 2+ messages in thread
From: Fabian Grünbichler @ 2025-08-13 7:34 UTC (permalink / raw)
To: pve-devel, Fiona Ebner
On Tue, 12 Aug 2025 17:30:14 +0200, Fiona Ebner wrote:
> Quoting Fabian Grünbichler from the bug report:
>
> > Intel ships some CPUs where the CPU address width and the IOMMU
> > address width are different, which requires setting that option to
> > properly support huge pages and/or VFIO:
> >
> > https://bugzilla.kernel.org/show_bug.cgi?id=220057
> > https://lore.kernel.org/all/20250502224035.3183451-1-alex.williamson@redhat.com/t
> > https://lore.kernel.org/qemu-devel/20250130134346.1754143-1-clg@redhat.com/
>
> [...]
Applied, thanks!
Note that there also is https://bugzilla.proxmox.com/show_bug.cgi?id=6608 which
is tangentially related and might be nice to fix, even though the user hasn't
reported back so far..
[1/1] close #6378: expose guest-phys-bits CPU option
commit: 2f3c741bfdffc49b50e17274bc25881a41f57ff7
Best regards,
--
Fabian Grünbichler <f.gruenbichler@proxmox.com>
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pve-devel mailing list
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^ permalink raw reply [flat|nested] 2+ messages in thread
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2025-08-12 15:30 [pve-devel] [PATCH qemu-server] close #6378: expose guest-phys-bits CPU option Fiona Ebner
2025-08-13 7:34 ` [pve-devel] applied: " Fabian Grünbichler
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