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[gnu.org, gitlab.com] Subject: [pve-devel] [PATCH pve-qemu 1/1] patch: add 0001-add-cpu-models-x86-64-abi.patch X-BeenThere: pve-devel@lists.proxmox.com X-Mailman-Version: 2.1.29 Precedence: list List-Id: Proxmox VE development discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 17 May 2023 07:03:27 -0000 Signed-off-by: Alexandre Derumier --- .../pve/0001-add-cpu-models-x86-64-abi.patch | 272 ++++++++++++++++++ debian/patches/series | 1 + 2 files changed, 273 insertions(+) create mode 100644 debian/patches/pve/0001-add-cpu-models-x86-64-abi.patch diff --git a/debian/patches/pve/0001-add-cpu-models-x86-64-abi.patch b/debian/patches/pve/0001-add-cpu-models-x86-64-abi.patch new file mode 100644 index 0000000..e98f862 --- /dev/null +++ b/debian/patches/pve/0001-add-cpu-models-x86-64-abi.patch @@ -0,0 +1,272 @@ +From 7d9ff48a96a7613a15e5427bc8987358e5529e45 Mon Sep 17 00:00:00 2001 +From: Alexandre Derumier +Date: Tue, 16 May 2023 11:36:19 +0200 +Subject: [PATCH] target/i386: define CPU models to model x86-64 ABI levels + +https://lists.gnu.org/archive/html/qemu-devel/2021-05/msg07807.html + +To paraphrase: + +https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterprise-linux-9-for-the-x86-64-v2-microarchitecture-level/ + +In 2020, AMD, Intel, Red Hat, and SUSE worked together to define +three microarchitecture levels on top of the historical x86-64 +baseline: + + * x86-64: original x86_64 baseline instruction set + * x86-64-v2: vector instructions up to Streaming SIMD + Extensions 4.2 (SSE4.2) and Supplemental + Streaming SIMD Extensions 3 (SSSE3), the + POPCNT instruction, and CMPXCHG16B + * x86-64-v3: vector instructions up to AVX2, MOVBE, + and additional bit-manipulation instructions. + * x86-64-v4: vector instructions from some of the + AVX-512 variants. + +This list of features is defined in the doc at: + + https://gitlab.com/x86-psABIs/x86-64-ABI/ + +QEMU has historically defaulted to the "qemu64" CPU model on +x86_64 targets, which is approximately the x86-64 baseline +ABI, with 'SVM' added. + +It is thought it might be desirable if QEMU could provide CPU models +that closely correspond to the ABI levels, while offering portability +across the maximum number of physical CPUs. + +Historically we've found that defining CPU models with an arbitrary +combination of CPU features can be problematic, as some guest OS +will not check all features they use, and instead assume that if +they see feature "XX", then "YY" will always exist. This is reasonable +in bare metal, but subject to breakage in virtualization. + +Thus in defining the CPU models for the ABI levels, this patch attempted +to base them off an existing CPU model. + +While each x86-64-abiNNN has a designated vendor, they are designed +to be vendor agnostic models. ie they are capable of running on any +physical x86_64 CPU model that satisfies the ABI level. eg although +the x86-64-abi2 model is based on Nehalem, it should be able to run +guests on an Opteron_G4/G5/EPYC host, since those CPUs support the +features required by the x86-64 v2 ABI. + +More precisely the models were defined as: + + * x86-64-abi1: close match for Opteron_G1, minus + vme + * x86-64-abi2: perfect match for Nehalem + * x86-64-abi3: close match of Haswell-noTSX, minus + aes pcid erms invpcid tsc-deadline + x2apic pclmulqdq + * x86-64-abi4: close match of Skylake-Server-noTSX-IBRS, minus + spec-ctrl + +None of the CPU models declare any VMX/SVM capability features. +IOW, even if a "vmx"/"svm" flag is added, it will still be unsafe +to attempt to live migrate the L1 guest if there are any L2 +guests running with hardware virtualization. + +Given their vendor agnostic design, these CPU models are primarily +thought tobe useful as the default CPU model for machine types. +QEMU upstream is quite conservative in mandating new hardware features, +but a downstream vendor may choose to mandate a newer x86-64 ABI level +for downstream only machine types. + +Note that TCG is not capable of supporting the 2 newest ABI levels +currently due to missing features: + +* x86-64-abi3: + + CPUID.01H:ECX.fma [bit 12] + CPUID.01H:ECX.avx [bit 28] + CPUID.01H:ECX.f16c [bit 29] + CPUID.07H:EBX.avx2 [bit 5] + +* x86-64-abi4: + + CPUID.01H:ECX.pcid [bit 17] + CPUID.01H:ECX.x2apic [bit 21] + CPUID.01H:ECX.tsc-deadline [bit 24] + CPUID.07H:EBX.invpcid [bit 10] + CPUID.07H:EBX.avx512f [bit 16] + CPUID.07H:EBX.avx512dq [bit 17] + CPUID.07H:EBX.rdseed [bit 18] + CPUID.07H:EBX.avx512cd [bit 28] + CPUID.07H:EBX.avx512bw [bit 30] + CPUID.07H:EBX.avx512vl [bit 31] + CPUID.80000001H:ECX.3dnowprefetch [bit 8] + CPUID.0DH:EAX.xsavec [bit 1] + +--- + target/i386/cpu.c | 162 ++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 162 insertions(+) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index 22b681ca3..294c20c53 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -1853,6 +1861,160 @@ static const X86CPUDefinition builtin_x86_defs[] = { + .xlevel = 0x8000000A, + .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, + }, ++ /* ++ * These first few CPU models are designed to satisfy the ++ * x86_64 ABI levels defined in: ++ * ++ * https://gitlab.com/x86-psABIs/x86-64-ABI/ ++ * ++ * They were constructed as follows: ++ * ++ * - Find all the CPU models which can satisfy the ABI ++ * - Calculate the lowest common denominator (LCD) of these ++ * models' features ++ * - Find the named model most closely matching the LCD ++ * - Strip its features back to the LCD ++ * ++ * The above spec uses the "x86-64-vNN" naming convention. ++ * This clashes with the "vNN" suffix QEMU uses for versioning. ++ * Thus we use "abiNNN" as a suffix. ++ */ ++ { ++ /* ++ * Derived from Opteron_G1, minus ++ * vme ++ */ ++ .name = "x86-64-abi1", ++ .level = 5, ++ .vendor = CPUID_VENDOR_AMD, ++ .family = 15, ++ .model = 6, ++ .stepping = 1, ++ .features[FEAT_1_EDX] = ++ CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | ++ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | ++ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | ++ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | ++ CPUID_DE | CPUID_FP87, ++ .features[FEAT_1_ECX] = ++ CPUID_EXT_SSE3, ++ .features[FEAT_8000_0001_EDX] = ++ CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, ++ .xlevel = 0x80000008, ++ .model_id = "QEMU x86-64 baseline ABI", ++ }, ++ { ++ /* Derived from Nehalem */ ++ .name = "x86-64-abi2", ++ .level = 11, ++ .vendor = CPUID_VENDOR_INTEL, ++ .family = 6, ++ .model = 26, ++ .stepping = 3, ++ .features[FEAT_1_EDX] = ++ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | ++ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | ++ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | ++ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | ++ CPUID_DE | CPUID_FP87, ++ .features[FEAT_1_ECX] = ++ CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_AES | ++ CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, ++ .features[FEAT_8000_0001_EDX] = ++ CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, ++ .features[FEAT_8000_0001_ECX] = ++ CPUID_EXT3_LAHF_LM, ++ .xlevel = 0x80000008, ++ .model_id = "QEMU x86-64-v2 ABI", ++ }, ++ { ++ /* ++ * Derived from Haswell-noTSX, minus ++ * pcid erms invpcid tsc-deadline x2apic pclmulqdq ++ */ ++ .name = "x86-64-abi3", ++ .level = 0xd, ++ .vendor = CPUID_VENDOR_INTEL, ++ .family = 6, ++ .model = 60, ++ .stepping = 1, ++ .features[FEAT_1_EDX] = ++ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | ++ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | ++ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | ++ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | ++ CPUID_DE | CPUID_FP87, ++ .features[FEAT_1_ECX] = ++ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | ++ CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | ++ CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | ++ CPUID_EXT_SSE3 | ++ CPUID_EXT_FMA | CPUID_EXT_MOVBE | ++ CPUID_EXT_F16C | CPUID_EXT_RDRAND, ++ .features[FEAT_8000_0001_EDX] = ++ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | ++ CPUID_EXT2_SYSCALL, ++ .features[FEAT_8000_0001_ECX] = ++ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, ++ .features[FEAT_7_0_EBX] = ++ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | ++ CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | ++ CPUID_7_0_EBX_BMI2, ++ .features[FEAT_XSAVE] = ++ CPUID_XSAVE_XSAVEOPT, ++ .features[FEAT_6_EAX] = ++ CPUID_6_EAX_ARAT, ++ .xlevel = 0x80000008, ++ .model_id = "QEMU x86-64-v3 ABI", ++ }, ++ { ++ /* ++ * Derived from Skylake-Server-noTSX-IBRS, minus: ++ * spec-ctrl ++ */ ++ .name = "x86-64-abi4", ++ .level = 0xd, ++ .vendor = CPUID_VENDOR_INTEL, ++ .family = 6, ++ .model = 85, ++ .stepping = 4, ++ .features[FEAT_1_EDX] = ++ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | ++ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | ++ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | ++ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | ++ CPUID_DE | CPUID_FP87, ++ .features[FEAT_1_ECX] = ++ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | ++ CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | ++ CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | ++ CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | ++ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | ++ CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, ++ .features[FEAT_8000_0001_EDX] = ++ CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | ++ CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, ++ .features[FEAT_8000_0001_ECX] = ++ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, ++ .features[FEAT_7_0_EBX] = ++ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | ++ CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | ++ CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | ++ CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | ++ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | ++ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | ++ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | ++ CPUID_7_0_EBX_AVX512VL, ++ .features[FEAT_7_0_ECX] = ++ CPUID_7_0_ECX_PKU, ++ .features[FEAT_XSAVE] = ++ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | ++ CPUID_XSAVE_XGETBV1, ++ .features[FEAT_6_EAX] = ++ CPUID_6_EAX_ARAT, ++ .xlevel = 0x80000008, ++ .model_id = "QEMU x86-64-v4 ABI", ++ }, + { + .name = "phenom", + .level = 5, +-- +2.30.2 + diff --git a/debian/patches/series b/debian/patches/series index 4e8ddd6..5273fab 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -94,3 +94,4 @@ pve/0059-vma-create-support-64KiB-unaligned-input-images.patch pve/0060-vma-create-avoid-triggering-assertion-in-error-case.patch pve/0061-block-alloc-track-avoid-premature-break.patch pve/0062-PVE-Backup-allow-passing-max-workers-performance-set.patch +pve/0001-add-cpu-models-x86-64-abi.patch \ No newline at end of file -- 2.30.2